LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4B IS
    PORT ( CLK  : IN STD_LOGIC;                  
           DOUT : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
END;
ARCHITECTURE DACC OF CNT4B IS
      SIGNAL Q1 : STD_LOGIC_VECTOR (3 DOWNTO 0); --设定内部节点作为地址计数器
    BEGIN

PROCESS(CLK )                                 
BEGIN
IF CLK'EVENT AND CLK = '1' THEN  
Q1<=Q1+1;  
END IF;         
END PROCESS;
DOUT<=Q1 ;
END;
