LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX IS
    PORT (SL,M1  : IN STD_LOGIC;
          QQ     : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  
          QOUT   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  
         MM0,MM1 : OUT STD_LOGIC     );
END MUX;
ARCHITECTURE behav OF MUX IS
 
 BEGIN
   
PROCESS (SL)  
     BEGIN
        IF SL = '1' THEN
        MM0 <= M1  ; MM1 <= '0' ;QOUT<=QQ;
        ELSE 
        MM0 <= '0' ; MM1 <= M1 ; 
        QOUT(3)<=QQ(0);
        QOUT(2)<=QQ(1);
        QOUT(1)<=QQ(2);
        QOUT(0)<=QQ(3);
           END IF;
   END PROCESS;

  
        
END behav;

