LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PW IS
    PORT (CLK,S : IN STD_LOGIC;
           Q  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
              );
END PW;
ARCHITECTURE behav OF PW IS
  SIGNAL QQ : STD_LOGIC_VECTOR(1 DOWNTO 0); 
 BEGIN
   PROCESS(QQ,S)  BEGIN
  IF S='1' THEN           
   CASE QQ IS
   WHEN "00" => Q<="0001";
   WHEN "01" => Q<="0010";
   WHEN "10" => Q<="0100";
   WHEN "11" => Q<="1000";
   WHEN OTHERS => Q<="0001";
   END  CASE;
   ELSE
   CASE QQ IS
   WHEN "00" => Q<="1000";
   WHEN "01" => Q<="0100";
   WHEN "10" => Q<="0010";
   WHEN "11" => Q<="0001";
   WHEN OTHERS => Q<="0001";
   END CASE ;
   END  IF;
 END PROCESS ;

 PROCESS (CLK)  
     BEGIN
        IF CLK'EVENT AND CLK = '1' THEN
             QQ <= QQ+1;
           END IF;
   END PROCESS;  
        
END behav;

