LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
    PORT (   D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        CLK ,EOC,RST : IN STD_LOGIC;
         ALE, START, OE, ADDA   : OUT STD_LOGIC;
         Q  : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
              );
END ADCINT;
ARCHITECTURE behav OF ADCINT IS
TYPE states IS (st0, st1, st2, st3,st4,st5,st6,st7) ; --定义各状态子类型
  SIGNAL current_state, next_state: states :=st0 ;
  --SIGNAL STS : STD_LOGIC_VECTOR(3 DOWNTO 0); 
  SIGNAL REGL 	    : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL LOCK	    : STD_LOGIC; -- 转换后数据输出锁存时钟信号
 BEGIN
    ADDA <= '0'; 
   PRO: PROCESS(current_state,EOC)  BEGIN  --规定各状态转换方式
   CASE current_state IS           
   WHEN st0 => ALE<='0';START<='0';OE<='0';LOCK<='0';next_state <= st1;
                     --初始态st --向下一状态st2转换，0809采样控制信号初始化
   WHEN st1=> ALE<='1';START<='0';OE<='0';LOCK<='0';next_state <= st2;  --启动采样信号STAR
   WHEN st2=> ALE<='1';START<='1';OE<='0';LOCK<='0';next_state <= st3;    --启动采样信号STAR
   WHEN st3=> ALE<='1';START<='1';OE<='0';LOCK<='0';   
     IF (EOC='0') THEN next_state <= st4; --EOC=0表明转换结束
	 ELSE next_state <= st3;               --转换结束未结束，继续等待
    END IF ;
   WHEN st4=> ALE<='0';START<='0';OE<='0';LOCK<='0';   
     IF (EOC='1') THEN next_state <= st5; --EOC=1表明转换结束
	 ELSE next_state <= st4;               --转换结束未结束，继续等待
    END IF ;
   WHEN st5=> ALE<='0';START<='1';OE<='1';LOCK<='0';next_state <= st6; --开启OE
   WHEN st6=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state <= st7; --开启数据锁存信号                                                  
   WHEN st7=> ALE<='0';START<='0';OE<='1';LOCK<='1';next_state <= st0; 
   WHEN OTHERS => ALE<='0';START<='0';OE<='0';LOCK<='0';next_state <= st0; 
   END CASE ;
 END PROCESS PRO ;

 PROCESS (CLK,RST)  
      BEGIN
    IF RST='1'  THEN  current_state <= st0;   
        ELSIF   CLK'EVENT AND CLK='1'  THEN   
          current_state <= next_state;
    END IF;

   END PROCESS; 

        PROCESS (LOCK) 
         BEGIN
        IF LOCK='1' AND LOCK'EVENT THEN   REGL <= D ;
        END IF;
       END PROCESS ; 
            Q <= REGL;
END behav;

